Status : Verified
| Personal Name | Quizon, Lawrence Roman A. |
|---|---|
| Resource Title | Rectangular Packing for High-utilization Analog In-Memory Compute Mappings |
| Date Issued | 15 July 2025 |
| Abstract | Analog in-memory computing (AIMC) accelerators offer exceptional energy and area efficiency for deep neural network (DNN) inference at the extreme edge, but their practical deployment is limited by low array utilization and high energy costs associated with weight writes on the typically energy-expensive nonvolatile memory cells. Existing DNN mappers typically map only a single matrix to the AIMC memory array at any given time, for simplicity. In this work, we introduce MARP, a new DNN mapping framework that leverages rectangular bin packing algorithms to maximize AIMC array utilization by packing multiple layers—across and within models—into a single memory array with interlayer weight reuse. We further present QRAcc, a fully integrated hybrid accelerator that contains both an SRAM-based AIMC accelerator and a weight-stationary digital accelerator, designed to exploit MARP’s mapping strategies. QRAcc achieves state-of-the-art energy efficiencies of 509.30 TOPS/W at 6.55 TOPS for AIMC and 81.36 TOPS/W at 57.6 GOPS for digital workloads. We demonstrate using the MLPerfTiny models that using MARP with QRAcc increases AIMC memory utilization by up to 64.7% (on ResNet-18 with any packer), reduces memory writes by up to 81.25% (on ResNet18 with the write-optimized MARP), increases energy efficiency by up to 1723.2% (on anomaly detection with FC-AE), lowers energy consumption by up to 59.52% (on anomaly detection with FC-AE), and lowers inference latency by up to 57.87% (on anomaly detection with FC-AE). The dense packings of QRAcc enable the mapping of larger models like MobileNetV2 on AIMC accelerators with many cores, such as NeuRRAM, which can fully map MobileNetV2 with only 34 out of 48 cores with MARP. MARP’s ability to reduce the number of AIMC memory writes to as much as 0.2x the original value is especially crucial for recently developed AIMC memory types that have high write energy costs, such as RRAM and PCM. MARP enables system-level energy effic |
| Degree Course | MS Electrical Engineering |
| Language | English |
| Keyword | AI accelerator; Design Space Exploration; Rectangular Packing |
| Material Type | Thesis/Dissertation |
Preliminary Pages
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Category : I - Has patentable or registrable invention of creation.
Access Permission : Limited Access